The invention relates generally to substrates for packaging microelectronic devices. In particular, the invention relates to substrates for packaging microelectronic devices that facilitate different I/O routing arrangements. Also provided are methods for packaging microelectronic devices, optionally in a flip-chip configuration.
Microelectronic device packages have been trending toward reduced package size and increased numbers of inputs and outputs (I/O). For example, chip-scale packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. CSPs typically include a microelectronic semiconductor device bonded, e.g., via wires or leads, to a substrate having contacts thereon. The substrate is typically only slightly larger than the device bonded thereto and has an increasingly finer contact pitch. The substrate contacts may have a pitch of 0.8 mm or less. In some instances, packages CSPs have as low as 0.4 mm pitch.
To reduce package size further, a flip-chip configuration may be employed. In this configuration, the front or contact-bearing surface of the microelectronic device faces towards a connection structure. Each contact on the device is joined by a solder bond to a corresponding contact pad on the connection structure, by positioning solder balls on the connection structure or device, juxtaposing the device with the connection structure in the front-face-down orientation, and momentarily reflowing the solder. Unlike the typical CSP configuration, wire or lead bonds are not required. As a result, the assembly occupies an area of the connection structure no larger than the area of the chip itself. In some instances, the substrate associated with a flip-chip package may have a smaller area than the device bonded thereto.
The flip-chip packaging configuration exhibits a number of advantages over other packaging configurations. For example, flip-chip configurations offer exceptional electrical performance, because eliminating bond wires may shorten the length of electrical paths by a factor of 25 to 100. In addition, the delaying inductance and capacitance of the connection may be reduced by a factor of 10. As a result, the flip-chip configuration provides a high-speed off-chip interconnection.
In addition, the flip-chip configuration is considered one of the most rugged mechanical interconnection configurations. Flip chips, when completed with an adhesive underfill, form durable solid blocks. They have been shown to withstand laboratory simulations of rocket liftoff and of artillery firing.
Furthermore, the flip-chip configuration can be the lowest cost interconnection for high volume automated production, with costs below $0.01 per connection. As a result, the flip-chip configuration is ubiquitous in the automotive industry as well as in low cost consumer watches. Furthermore, the flip-chip configuration is gaining popularity in smart cards, radio frequency identification (RF-ID) devices, cellular telephones, and other cost-dominated applications.
Notably, the flip-chip configuration provides a high degree of I/O connection flexibility. When wire bond connections are used, they may be limited to the perimeter of the die, driving die sizes up as the number of connections increases. In contrast, flip-chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Area connections also allow 3-D stacking of microelectronic devices and other components. For example, devices having substantially similar functionality, e.g., memory chips, may be packaged together to provide greater capacity, increased speed, and/or improved performance. Patents describing stacked packaging of microelectronic devices include, for example, U.S. Pat. Nos. 5,861,666, 6,121,676, 6,225,688, 6,465,893, and 6,699,730.
A wide range of flip-chip materials, equipment, and service providers is available. For example, rigid laminate substrates have been used to package microelectronic devices. Such substrates may include two to four alternating layers fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. bismaleimide triazine (BT) may also be incorporated in such substrates to provide greater thermal stability. In addition, metal-clad tapes of copper-on-polyimide are commonly used for fine-line and high-density electronic interconnection applications.
The flip-chip packaging configuration requires a substrate having conductive regions on a surface thereof that corresponds to the contact pattern of the device to be bonded thereto. Thus, current practice requires a uniquely designed substrate for any particular microelectronic device. In addition, in stacked packages of identical or similar microelectronic devices, unique I/O routing may be achieved through different techniques such as wire-bond, trace break, trace join, and etc. Of course, each substrate can be uniquely designed, but uniquely designed substrates increases package cost.
Accordingly, there exist opportunities in the art to provide alternatives and improvements to substrate technologies for compact microelectronic device packaging applications, particularly those technologies compatible with rigid bonding techniques associated with the flip-chip configuration and those technologies that require versatile I/O routing arrangements.